Thank you all for your replies, they are very helpful.
I might have found a better solution though: run the RP2040 using the standard 12.0000MHz crystal or oscillator setup, and feed one of the clk_gpout to YMF825.
I was reading section 2.15.3. Clock Generators of the RP2040 datasheet. Turns out RP2040 is capable of generating clock signal of variable frequency on GPIO0-GPIO3. If my understanding is correct, this clock is subdivided from the PLL source? That could mean it has fine granularity and we can get close enough to 12.2880MHz?
(My goal is not to make the two ICs run exactly in sync, I am merely trying to save cost by using 1 less crystal in my design)
Please confirm that I haven't misread the datasheet. If this is indeed possible, how do I set it up software-side?
Cheers,
David
I might have found a better solution though: run the RP2040 using the standard 12.0000MHz crystal or oscillator setup, and feed one of the clk_gpout to YMF825.
I was reading section 2.15.3. Clock Generators of the RP2040 datasheet. Turns out RP2040 is capable of generating clock signal of variable frequency on GPIO0-GPIO3. If my understanding is correct, this clock is subdivided from the PLL source? That could mean it has fine granularity and we can get close enough to 12.2880MHz?
(My goal is not to make the two ICs run exactly in sync, I am merely trying to save cost by using 1 less crystal in my design)
Please confirm that I haven't misread the datasheet. If this is indeed possible, how do I set it up software-side?
Cheers,
David
Statistics: Posted by fengshuo — Tue Jul 16, 2024 12:42 pm